发明名称
摘要 A semiconductor memory device is constituted such that, when a first wiring layer provides a bit line of a first common complementary data line pair and a third wiring layer provides a bit line of a second common complementary data line pair, a second wiring layer makes an overlapped area between the bit line and the bit bar line of the second common complementary dada line pair equal to the bit line of the first common complementary data line pair and also an overlapped area between the bit line and the bit bar line of the first common complementary data line pair equal to the bit line of the second common complementary data line pair.
申请公布号 JP3599970(B2) 申请公布日期 2004.12.08
申请号 JP19970253806 申请日期 1997.09.18
申请人 发明人
分类号 H01L21/3205;G11C5/06;H01L21/8242;H01L23/52;H01L27/108 主分类号 H01L21/3205
代理机构 代理人
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