Dicing process for GAAS/INP and other semiconductor materials

摘要

A semiconductor wafer and a method for fabricating a semiconductor wafer having improved dicing lanes are provided. The dicing lanes include grooves formed by photolithography and etching processes. The wafer also includes a plating layer on a back side of the wafer to facilitate bonding of individual circuit chips to a suitable substrate and to effect efficient heat transfer between the chip and the substrate. Photolithography and etching processes are employed to etch horizontal and vertical lanes in the plating layer to facilitate breaking of the individual chips from the wafer. The horizontal and vertical lanes etched in the plating layer are coincident to the grooves etched in the substrate. The wafer can then be broken into individual circuit chips by applying stress to the back of the wafer, such that the wafer cleanly breaks along the horizontal and vertical dicing lanes and the etched grooves.