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发明名称
积体电路时脉网路电容的最佳化
摘要
本发明提供了一种积体电路时脉网路电容最佳化方法,其特征在于,该方法包括识别时脉走线和信号走线之间跨接点,在跨接点处将时脉走线电容减小到参考走线电容。每一时脉走线均由布线在该时脉走线两侧的接地走线遮罩。时脉走线电容减小到参考走线电容的方法包括在识别出的跨接点处减小参考走线之宽度。在跨接点处减小参考走线宽度操作可减小电容以抵消时脉走线与信号走线之间的附加电容。透过在跨接点处修整走线或开刻槽方式实现宽度减小之目的。这种电容补偿方式可为时脉网路中的时脉走线提供实质上均匀的单位长度电容。
申请公布号
TW200426560
申请公布日期
2004.12.01
申请号
TW092127914
申请日期
2003.10.08
申请人
智权第一公司
发明人
雷蒙 伯特兰;伊莉莎白 隆威尔;金 朗伯格
分类号
G06F1/08
主分类号
G06F1/08
代理机构
代理人
詹铭文;萧锡清
主权项
地址
美国
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