发明名称 |
Programmable memory devices with latching buffer circuit and methods for operating the same |
摘要 |
Programmable memory devices include a memory cell having an associated bit line. A buffer circuit couples the bit line to a data line. The buffer circuit has a sense node coupled to the bit line and includes a latch circuit having a latch node coupled to the data line. A control circuit resets the latch node between a program operation of the memory cell and its corresponding program-verify operation. The memory devices may be NAND-type flash memory devices and the memory cell may be one of a string of memory cells connected in series between the bit line and a common source line. A transistor may couple the data line to the latch node and a transistor may couple the latch node to the sense node. Methods of operating the same are also provided.
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申请公布号 |
US6826082(B2) |
申请公布日期 |
2004.11.30 |
申请号 |
US20030403739 |
申请日期 |
2003.03.31 |
申请人 |
SAMSUNG ELECTRONICS CO., LTD. |
发明人 |
HWANG SANG-WON;LEE SUNG-SOO |
分类号 |
G11C16/02;G11C7/06;G11C16/24;(IPC1-7):G11C16/04 |
主分类号 |
G11C16/02 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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