发明名称 |
Buffering data transfer between a chipset and memory modules |
摘要 |
Buffering data transfer between a chipset and memory modules is disclosed. The disclosure includes providing and configuring at least one buffer. The buffers are provided in an interface between a chipset and memory modules. The buffers allow the interface to be split into first and second sub-interfaces. The first sub-interface is between the chipset and the at least one buffer. The second sub-interface is between the at least one buffer and the memory modules. The buffers are then configured to properly latch the data being transferred between the chipset and the memory modules. The first and second sub-interfaces operate independently but in synchronization with each other.
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申请公布号 |
US6820163(B1) |
申请公布日期 |
2004.11.16 |
申请号 |
US20000666489 |
申请日期 |
2000.09.18 |
申请人 |
INTEL CORPORATION |
发明人 |
MCCALL JAMES A.;BONELLA RANDY M.;HALBERT JOHN B.;DODD JIM M.;LAM CHUNG |
分类号 |
G06F3/00;G06F12/00;G06F13/00;G06F13/42;G11C7/10;(IPC1-7):G06F13/00 |
主分类号 |
G06F3/00 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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