发明名称 Clock recovery circuit
摘要 A circuit is provided for clock recovery from a specified datastream. The circuit includes a reference extraction unit for extracting from the datastream time references defining a reference time base, and a digital Phase Locked Loop coupled to the reference extraction unit. The digital Phase Locked Loop includes a first programmable counter in the guise of a digitally controlled oscillator for overseeing an output time base, a second programmable counter in the guise of a loop divider for overseeing a loop time base, and a dedicated processor capable of executing a program. The program includes a first software module in the guise of a phase comparator for comparing values of the loop time base and the reference time base and generating a loop error; and a second software module in the guise of a loop filter for producing an adaptation value of an increment value of the first programmable counter from the loop error. Also provided are a user terminal for an interactive telebroadcasting system that includes at least one such circuit for clock recovery, and a method for clock recovery from a specified datastream.
申请公布号 US2004223578(A1) 申请公布日期 2004.11.11
申请号 US20040841705 申请日期 2004.05.07
申请人 STMICROELECTRONICS SA 发明人 LAGARDE JEAN-PIERRE
分类号 H03D3/24;H03L7/099;H03L7/197;H04L7/033;H04N7/173;(IPC1-7):H03D3/24 主分类号 H03D3/24
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