发明名称 Single clock source for plural scan capture chains
摘要 A clock signal is applied to a clock pin of an integrated circuit. The clock signal is coupled from the clock pin to a first scan chain in a first time period without coupling the clock signal to a second scan chain during the first time period. The clock signal is coupled from the clock pin to the second scan chain during a second time period without coupling the clock signal to the first scan chain during the second time period.
申请公布号 US6815978(B1) 申请公布日期 2004.11.09
申请号 US20030419433 申请日期 2003.04.21
申请人 INTEL CORPORATION 发明人 YAROM ITAI
分类号 G01R31/3185;G06F1/08;G06F1/10;(IPC1-7):H03K19/173 主分类号 G01R31/3185
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