发明名称 |
MICROPROCESSOR INCLUDING CACHE MEMORY SUPPORTING MULTIPLE ACCESSES PER CYCLE |
摘要 |
<p>A microprocessor including a level two cache memory which supports multiple accesses per cycle. The microprocessor includes an execution unit coupled to a cache memory subsystem which includes a cache memory coupled to a plurality of buses. The cache memory includes a plurality of independently accessible storage blocks. The buses may be coupled to convey a plurality of cache access requests to each of the storage blocks. In response to the plurality of cache access requests being conveyed on the plurality of cache buses, different ones of the storage blocks are concurrently accessible.</p> |
申请公布号 |
WO2004049171(A3) |
申请公布日期 |
2004.11.04 |
申请号 |
WO2003US35280 |
申请日期 |
2003.11.06 |
申请人 |
ADVANCED MICRO DEVICES INC |
发明人 |
ALSUP MITCHELL |
分类号 |
G06F12/08;(IPC1-7):G06F12/08 |
主分类号 |
G06F12/08 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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