发明名称 |
Method for fabricating memory cell structure employing contiguous gate and capacitor dielectric layer |
摘要 |
A method for fabricating a memory cell structure provides for fabricating a capacitor within the memory cell structure within an asymmetric trench within an isolation region adjoining an active region such that a capacitor node layer within the capacitor contacts a sidewall of the active region and is electrically connected to a source/drain region within a field effect transistor device fabricated within the active region. The method also employs when fabricating the memory cell structure a contiguous dielectric layer as a gate dielectric layer within the field effect transistor device and a capacitor dielectric layer within the capacitor. The dynamic random access memory cell structure may be efficiently fabricated as an embedded dynamic random access memory cell structure.
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申请公布号 |
US6812093(B2) |
申请公布日期 |
2004.11.02 |
申请号 |
US20030401429 |
申请日期 |
2003.03.28 |
申请人 |
TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD |
发明人 |
TU KUO-CHI |
分类号 |
H01L21/02;H01L21/334;H01L21/8242;H01L27/108;H01L29/94;(IPC1-7):H01L21/824 |
主分类号 |
H01L21/02 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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