发明名称 Method and apparatus for processing blocks in a pipeline
摘要 Method in a pipeline processing stage in a processor, includes the steps of: receiving a first block from a first register and a first execution parameter associated with the first block from a second register, the execution parameter having a first value; inspecting a set of data being at least a part of the first block; and, if the set of data differs from a predetermined condition, storing a second execution parameter on a third register and a third execution parameter on the first register, where the second execution parameter has a second value and is associated with the first block and the third execution parameter has the first value and will be associated with a second block. The invention also relates to the pipeline processor, a module, an integrated circuit and a computer unit.
申请公布号 US2004215620(A1) 申请公布日期 2004.10.28
申请号 US20040478377 申请日期 2004.05.07
申请人 SVENSSON LARS-OLOV;STROMQVIST THOMAS;NORDMARK GUNNAR;WESTLUND PAR;ROOS JOACHIM 发明人 SVENSSON LARS-OLOV;STROMQVIST THOMAS;NORDMARK GUNNAR;WESTLUND PAR;ROOS JOACHIM
分类号 H04L12/56;(IPC1-7):G06F7/00 主分类号 H04L12/56
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