发明名称 |
Complete refresh scheme for 3T dynamic random access memory cells |
摘要 |
A refresh scheme for a semiconductor memory macro that comprises three-transistor dynamic random access memory (3T-DRAM) cells. Similar to an internal refresh operation, an external access command is also interpreted as a read-then-write operation. A clock cycle is partitioned as a plurality of time slots by an internal clock generator. Each time slot is assigned to execute a specific memory cell operations, whereby array idle time typically needed for performing exclusively non-array operations is no longer required. An external access and an internal refresh can be operated sequentially without degrading speed performance. An internal refresh can occur in every clock cycle period to retain the stored data. This clock cycle period is less than the time required for consecutively performing the external access and thereafter the internal refresh upon the completion of the external access.
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申请公布号 |
US6809979(B1) |
申请公布日期 |
2004.10.26 |
申请号 |
US20030379859 |
申请日期 |
2003.03.04 |
申请人 |
FERNANDEZ & ASSOCIATES, LLP |
发明人 |
TANG ROBIN |
分类号 |
G11C11/405;G11C11/406;(IPC1-7):G11C7/00 |
主分类号 |
G11C11/405 |
代理机构 |
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代理人 |
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地址 |
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