| 摘要 |
The invention relates to a capacitor arrangement in a semiconductor layout, comprising capacitors formed on a substrate (1) by a first layer (2', 2'') of a conductive material and a second layer (3', 3'') of a conductive material with an insulating material (4) in between said first (2', 2'') and said second (3', 3'') layer of conducting material. In order to improve the design of such an arrangement, it is proposed that for each desired ideal capacitor (C1-C4), a pair of a first and a second capacitor (C1'-C4', C1''-C4'') is provided. The first and second capacitor (C1'-C4', C1''-C4'') of each pair are connected in a way offering a pair of terminals, at each of which terminals of a respective pair of terminals an essentially equal parasitic capacitance (Csub) formed between first layers (2', 2'') of conductive material and said substrate (1) is achieved. The invention equally relates to a method for producing such an arrangement.
|
