发明名称 |
SEMICONDUCTOR MEMORY DEVICE |
摘要 |
PROBLEM TO BE SOLVED: To provide a semiconductor memory device in which defect detection can be performed in a short period oftime and the circuit area is small. SOLUTION: A bit line equalizer circuit 30a equalizes respectively bit lines BL to a bit line potential VBLA and bit lines /BL to a bit line potential VBLB in accordance with activation of a bit line equalizing signal BLEQ. A read error in which a short circuit of WL-BC(BL) and a short circuit of WL-SC(SN) are reflected can be detected more quickly without increasing the circuit area by setting the bit lines potential VBLA for the bit lines BL higher than the bit lines potential VBLB for the bit lines /BL. COPYRIGHT: (C)2005,JPO&NCIPI
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申请公布号 |
JP2004288299(A) |
申请公布日期 |
2004.10.14 |
申请号 |
JP20030079965 |
申请日期 |
2003.03.24 |
申请人 |
RENESAS TECHNOLOGY CORP |
发明人 |
HORIBATAKE SHUICHI;TOMIUE KENJI |
分类号 |
G01R31/28;G06F15/00;G11C7/12;G11C11/401;G11C11/4094;G11C29/00;G11C29/02;G11C29/06;G11C29/50;(IPC1-7):G11C29/00 |
主分类号 |
G01R31/28 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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