| 摘要 |
PURPOSE: A method for forming a test pattern of a semiconductor device is provided to improve integration degree by reducing the area of the test pattern and to prevent abnormal failure by using a current tab as a heat sink. CONSTITUTION: The first lower line(33a) of a main part and the second lower line(33b) of a current tap part are formed on a substrate with a lower layer(31). An interlayer dielectric(35) is formed on the resultant structure. A plurality of contact holes(37a,37b,37c) are formed to expose the first and second lower line by selectively etching the interlayer dielectric. Tungsten plugs(39a,39b,39c) are formed in the contact holes. The first, second and third upper line(41) are formed to connect electrically the first and second lower line. A metal pad(43) is formed on the upper lines.
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