发明名称 PLL circuit and recording and playback apparatus using same
摘要 A PLL circuit functioning as a clock recovery circuit in a tape recording and playback apparatus employing the PRML method has a level determining circuit for detecting that head output level (signal level) is at or lower than a certain level during track crossing for a high-speed search, and effects a hold on a loop filter according to a level determination output to thereby hold PLL operation, whereby the PLL behavior is not disturbed by a noise component occurring during track crossing. Thus, it is possible to stabilize search operation and increase the design margin.
申请公布号 US6804074(B2) 申请公布日期 2004.10.12
申请号 US20010862422 申请日期 2001.05.23
申请人 SONY CORPORATION 发明人 SHOJI NORIO;SUGITA JUNKICHI;SENBA KIMIMASA;KAWAKUBO TOSHIHIRO
分类号 G11B20/14;H03L7/08;H03L7/091;H03L7/14;(IPC1-7):G11B5/09;H03L7/06 主分类号 G11B20/14
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