发明名称 System and method of processing memory requests in a pipelined memory controller
摘要 A method for processing multiple memory requests in a pipeline. Each memory request is processed in part by a plurality of stages. In a first stage, the memory request is decoded. In a second stage, the address information for the memory request is processed. In a third stage, the data for the memory request is transferred. A request buffer is used to hold each of the memory requests during the processing of each of the memory requests.
申请公布号 US2004199739(A1) 申请公布日期 2004.10.07
申请号 US20040830872 申请日期 2004.04.23
申请人 JEDDELOH JOSEPH 发明人 JEDDELOH JOSEPH
分类号 F02M27/06;F02M31/14;G06F9/38;(IPC1-7):G06F12/00 主分类号 F02M27/06
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