| 摘要 |
Input data (plain text data or encrypted text data) are latched according to a clock CLK1 and, after initial transposition thereof, the data are outputted from a selector 62. The lower-order bits of the output data from the selector 62 are processed through expanded transposition and then are calculated together with key data K1 in an XOR circuit, and the result data are latched according to a clock CLK2. The latched 48-bit data are divided into eight 6-bits data, each of which is then replaced with 4-bit data, and after combination thereof, the data are transposed. In the calculations of second and subsequent stages, the data obtained through replacement and combination in a replacement/combination circuit 66 are latched according to the clock CLK1 and then are outputted from the selector 62. And after completion of the 16th-stage calculation, the data replaced in a replacement circuit 67 are inversely transposed, hence realizing an improved encryption/decryption calculating device where the power consumption is remarkably decreased and the circuit scale is reducible.
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