发明名称 Lot-optimized wafer level burn-in
摘要 Embodiments disclosed relate to wafer level burn-in of integrated circuits on a semiconductor wafer. One embodiment disclosed performs monitored burn-in on sample wafers from a manufactured lot of wafers and determines a burn-in time for the lot from results of the monitored burn-in. The burn-in on remaining wafers from the lot is then performed for the burn-in time that was determined. Another embodiment disclosed performs burn-in on wafers from a manufactured lot of wafers while monitoring in real-time the burn-in for a subset of wafers in the lot. Using fallout data from the real-time monitoring, a determination is made as to whether the burn-in time is sufficient. If the burn-in time is determined to be sufficient, then the burn-in of the lot is stopped.
申请公布号 US6800495(B2) 申请公布日期 2004.10.05
申请号 US20020251091 申请日期 2002.09.20
申请人 CYPRESS SEMICONDUCTOR CORPORATION 发明人 PAYAN CESAR;JIN BO
分类号 G01R31/28;(IPC1-7):H01L21/66 主分类号 G01R31/28
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