| 摘要 |
PROBLEM TO BE SOLVED: To provide an EEPROM with a selecting transistor and a method of manufacturing the same. SOLUTION: The element has a cell gate pattern WLn and selector gate patterns GSL, SSL which are arranged on a semiconductor substrate and are isolated from one another. The cell gate pattern WLn comprises a tunnel oxide film 58a, a floating gate 60f, first gate inter layer dielectric films 62a, 64a, and a controlling gate electrode 68a, which are sequentially laminated on the semiconductor substrate. The selecting gate patterns GSL, SSL comprise a gate oxide film 58b, a lower gate pattern 60b, second gate inter layer dielectric films 62b, 64b, and a upper gate pattern 68b, which are sequentially laminated on the semiconductor substrate. The second gate inter layer dielectric films 62b, 64b, whose widths are narrower than the widths of the selecting gate patterns GSL, SSL, are extended laterally from one side wall of the selecting gate patterns toward the center and are intervened between portions of the upper gate pattern 68b and the lower gate pattern 60b. COPYRIGHT: (C)2004,JPO&NCIPI
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