NET LIST GENERATION SYSTEM AND METHOD FOR DELAY SIMULATION IN SEMICONDUCTOR INTEGRATED CIRCUIT

摘要

PROBLEM TO BE SOLVED: To provide a generation system and method of a net list for delay simulation capable of executing a highly precise delay simulation in a block level even to a largely scaled block. SOLUTION: This system comprises a delay model generating means 5 for generating a delay model file 6 from an LPE net list 2, a net generating means 7 for delay simulation for generating a net list for delay simulation from a pre-layout network list 1 and a processing control means 4 for executing control corresponding to the contents of a control file 3. A delay model file 6 generated from the LPE net list 2 by the delay model generating means 5 is reflected on the pre-layout net list 1 so that a net list 8 for delay simulation can be generated. COPYRIGHT: (C)2004,JPO&NCIPI