发明名称 |
Universal clock generator using delay lock loop |
摘要 |
A clock generator and method generates a plurality of clocks of different frequencies using a delay lock loop and a sequencer. The delay lock loop receives an input clock signal having an input clock frequency and generates a plurality of delayed clock signals each having a frequency same as the input clock frequency and a different phase delay in relation to the input clock signal. The sequencer receives the delayed clock signals and selects one the delayed clock signals at any moment according to a predetermined sequence to generate an output clock signal having an output clock frequency corresponding to the predetermined sequence. The frequency of the output clock signal is controlled by the sequence in which the delayed clock signals are by the sequencer.
|
申请公布号 |
US6798266(B1) |
申请公布日期 |
2004.09.28 |
申请号 |
US20030446233 |
申请日期 |
2003.05.27 |
申请人 |
MICREL, INCORPORATED |
发明人 |
VU CUNG;CHANG MENPING;CHEN JUNE-YING |
分类号 |
G06F1/06;H03L7/081;(IPC1-7):G06F1/04 |
主分类号 |
G06F1/06 |
代理机构 |
|
代理人 |
|
主权项 |
|
地址 |
|