发明名称 |
PEAK POTENTIAL DETECTING CIRCUIT, BOTTOM POTENTIAL DETECTING CIRCUIT, AND DIGITAL SLICE CIRCUIT |
摘要 |
PROBLEM TO BE SOLVED: To detect highly accurately the peak potential of a signal input terminal even when the peak potential changes slowly. SOLUTION: A peak potential detecting circuit has: a capacitor CH1; a first charging circuit for connecting a power source potential VDD and a peak potential output terminal only when the potential IN of a signal input terminal is larger than the potential OUTX of the peak potential output terminal and charging the capacitor CH1; and a first discharging circuit for connecting a second bias potential bias 2 which is smaller than the minimum value to which the peak potential of the signal input terminal can reach and the peak potential output terminal only when the potential IN of the signal input terminal is larger than a first bias potential bias 1 which is smaller than the minimum value to which the peak potential of the signal input terminal can reach and discharging the capacitor CH1. COPYRIGHT: (C)2004,JPO&NCIPI
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申请公布号 |
JP2004265522(A) |
申请公布日期 |
2004.09.24 |
申请号 |
JP20030055206 |
申请日期 |
2003.03.03 |
申请人 |
NIPPON TELEGR & TELEPH CORP <NTT> |
发明人 |
UGAJIN MAMORU;TSUKAHARA TSUNEO |
分类号 |
G11C27/00;(IPC1-7):G11C27/00 |
主分类号 |
G11C27/00 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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