发明名称 SEMICONDUCTOR INTEGRATED CIRCUIT, AND ITS LAYOUT DESIGN METHOD
摘要 PROBLEM TO BE SOLVED: To improve a slew rate without changing a netlist in layout design of a semiconductor integrated circuit including a network with many branches. SOLUTION: The layout design method is provided with a step S2 of inputting the netlist including a first circuit outputting a signal and a plurality of second circuits operating on the basis of the signal outputted from the first circuit, a step S 3 of carrying out automatic arrangement and wiring of a circuit included in the netlist so that an output terminal of the first circuit is connected to an input terminal of the second circuit by wiring having at least one branch point on the basis of the netlist, and a step S4 of respectively inserting a plurality of buffer circuits within a predetermined distance from any one of the branch points between at least one branch point and the input terminals of the plurality of second circuits. COPYRIGHT: (C)2004,JPO&NCIPI
申请公布号 JP2004265071(A) 申请公布日期 2004.09.24
申请号 JP20030054005 申请日期 2003.02.28
申请人 SEIKO EPSON CORP 发明人 KURASHIMA KENJI
分类号 G06F17/50;H01L21/82;H01L27/118;(IPC1-7):G06F17/50 主分类号 G06F17/50
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