发明名称 DESIGN METHOD AND VERIFYING METHOD FOR LSI
摘要 <p><P>PROBLEM TO BE SOLVED: To increase the secrecy of circuit design data higher than a conventional one by using encryption processing in the design of an LSI and to verify encrypted design data while maintaining their secrecy. <P>SOLUTION: In encryption processing SA, the encryption of circuit design data 11 requiring secrecy is carried out, and encrypted design data 12 and a decoding key 13 are created. The encrypted design data 12 are provided to a user executing designing/verifying processing S2, and the key 13 is also provided if necessary. In the designing/verifying processing SB, various kinds of processings are carried out on the encrypted design data 12 while keeping original contents of the circuit secret. In decoding processing SC, decoding of the encrypted design data 14 after the execution of the designing/verifying processing S2 is carried out, and the original circuit design data 15 are created. <P>COPYRIGHT: (C)2004,JPO&NCIPI</p>
申请公布号 JP2004265437(A) 申请公布日期 2004.09.24
申请号 JP20040117293 申请日期 2004.04.12
申请人 MATSUSHITA ELECTRIC IND CO LTD 发明人 SHIOMI KENTARO;MOTOHARA AKIRA;FUJIWARA MUTSUMI;YOKOYAMA TOSHIYUKI;FUJIMURA KATSUYA
分类号 G06F21/24;G06F12/14;G06F17/50;G06F21/06;(IPC1-7):G06F17/50 主分类号 G06F21/24
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