| 摘要 |
<p><P>PROBLEM TO BE SOLVED: To provide a nonvolatile semiconductor memory having a small layout size. <P>SOLUTION: A memory cell array 4000 arranged with a plurality of memory cells 410 in the row direction X and the column direction Y comprises a source line diffusion layer SLD formed continuously by connecting the plurality of memory cells 410 commonly along the row direction X, a bit line diffusion layer BLD, a region 900 for isolating the bit line diffusion layer BLD, and a word gate common connecting part 55. Each of the plurality of memory cells 410 includes a word gate 412 and a select gate 411, the bit line diffusion layer BLD is provided between two word gates 412 adjacent in the column direction Y, and the word gate common connecting part 55 connects the two word gates 412 commonly in the upper layer of the isolation region 900. <P>COPYRIGHT: (C)2004,JPO&NCIPI</p> |
