发明名称 |
JITTER SUPPRESSION CIRCUIT |
摘要 |
<p><P>PROBLEM TO BE SOLVED: To provide a jitter suppression circuit capable of suppressing the occurrence of an overshoot and satisfying a standard. <P>SOLUTION: The jitter suppression circuit for clocks in a synchronous transmission line network comprises: an offset request circuit for detecting that the data read position of a buffer memory storing the data of main signals is in an area close to the center of the buffer memory and generating a first offset request and also detecting that the data read position is present in an area away from the center of the buffer memory and generating a second offset request; and an offset instruction part for instructing offset when the first offset request outputted from the buffer memory is generated continuously for a prescribed number of times or when the second offset request is generated. <P>COPYRIGHT: (C)2004,JPO&NCIPI</p> |
申请公布号 |
JP2004260448(A) |
申请公布日期 |
2004.09.16 |
申请号 |
JP20030047797 |
申请日期 |
2003.02.25 |
申请人 |
FUJITSU LTD |
发明人 |
MAKISHIMA HIROMICHI;OBANA YUJI;KAWAHARA EIGO;FUJIMOTO HISANOBU;SHIODA MASAHIRO |
分类号 |
H04J3/00;H04L7/00;(IPC1-7):H04J3/00 |
主分类号 |
H04J3/00 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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