发明名称 METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE
摘要 PROBLEM TO BE SOLVED: To solve the problems of the decrease of a gate breakdown voltage or the increase of gate leakage current due to the arrival at a gate insulating layer interface, by diffusing a transition metal element along the grain boundary of a polycrystal at a silicide gate electrode forming time by thinning a gate insulating layer in association with the microminiaturization of a MOS device. SOLUTION: A method for manufacturing a semiconductor device includes a step of forming an Si polycrystal layer on the gate insulating layer, a step of patterning an ion implantation inhibiting layer on the Si polycrystal layer, a step of making the Si polycrystal layer of the periphery of the ion implantation inhibiting layer amorphous by retaining the Si polycrystal layer of the lower part of the ion implantation inhibiting layer by implanting amorphous region forming ion on the Si polycrystal layer from a direction inclined with respect to the vertical direction on the front surface of the Si polycrystal layer, and a step of recrystallizing the Si polycrystal layer which is made amorphous by heat treating. COPYRIGHT: (C)2004,JPO&NCIPI
申请公布号 JP2004259788(A) 申请公布日期 2004.09.16
申请号 JP20030046600 申请日期 2003.02.24
申请人 FUJITSU LTD 发明人 KODAMA SHIGEO
分类号 H01L21/28;H01L21/265;H01L21/266;H01L29/423;H01L29/49;H01L29/78;(IPC1-7):H01L21/28 主分类号 H01L21/28
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