发明名称 Method for fabricating a MOSFET and reducing line width of gate structure
摘要 A method for fabricating a MOSFET is provided. The method comprises: providing a substrate, the substrate having a gate structure; forming a drain region and a source region in the substrate, the drain region and the source region being on two sides of the gate structure respectively; forming a metal suicide layer on the surface of the gate structure, the drain region, and the source region; forming a patterned block on the metal silicide layer above the gate structure, and forming a first dielectric layer above the substrate except the gate strcutre, the patterned block being formed above the center of the gate structure and the metal silicide layer above the gate structure beside two sides of the patterned block being exposed; removing a portion of the metal silicide layer and a portion of the gate structure by using the patterned block as a mask; and forming a drain extension region and a source extension region in the substrate, beside two sides of the remaining gate structure.
申请公布号 US6790720(B1) 申请公布日期 2004.09.14
申请号 US20030605360 申请日期 2003.09.25
申请人 MACRONIX INTERNATIONAL CO., LTD. 发明人 LAI ERH-KUN
分类号 H01L21/28;H01L21/336;H01L29/78;(IPC1-7):H01L21/336;H01L21/320 主分类号 H01L21/28
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