| 摘要 |
PROBLEM TO BE SOLVED: To provide an internal data bus drive circuit and an external data bus drive circuit inside a custom LSI, capable of coping with high-speed reading of a microcomputer with a small occupying area on an integrated circuit. SOLUTION: A PMOS transistor between a power source and each bit line of an internal data bus sets the bit line to an H level when a read enable signal is in an L level. The internal data bus drive circuit has an NMOS transistor between the bit line and a ground, and the NMOS transistor is electroconducted to set the bit line to an L level when the PMOS transistor is not electroconducted and when transmission data are in an L level. A data latch of the external data bus drive circuit is reset during an L level of a read signal, and a signal formed by inverting a signal of the internal data bus is latched at time when a prescribed time lapses from the rising of the read signal. A 3-state non-inverting driver drives a bit line of an external data bus corresponding to a signal formed by inverting an output signal of the data latch only during an H level of the read signal. COPYRIGHT: (C)2004,JPO&NCIPI
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