| 摘要 |
Counter-based duty cycle correction (DCC) circuits and methods. A first counter is periodically enabled to count for one input clock period. After completion of the count, the result is divided by two and stored in a register. Thus, the value stored in the register represents a point halfway through the input clock period. Each time the input clock signal changes from a first state to a second state, an output clock generator also changes the output clock signal from the first state to the second state, and the second counter is enabled. A comparator compares the value in the second counter to the value stored in the register. When the second counter has reached the value stored in the register, the half-way point of the input clock cycle has been reached, and the output clock generator changes the output clock signal from the second state back to the first state.
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