发明名称 |
PHASE CHANGE MEMORY ARRAY |
摘要 |
A phase change memory includes a plurality of word lines, a plurality of bits lines intersecting the word lines, and a plurality of memory cells arranged in rows along the word lines and located at corresponding intersection regions of the word lines and bit lines. Each of the memory cells includes a cell transistor having a gate connected to a corresponding word line, and a resistor and a phase change cell connected in series between a drain of the cell transistor and a corresponding bit line. In order to increase a cell drive current, the phase change memory also includes a plurality of auxiliary transistors respectively connected between the drains of the cell transistors of adjacent said memory cells.
|
申请公布号 |
US2004170053(A1) |
申请公布日期 |
2004.09.02 |
申请号 |
US20040786303 |
申请日期 |
2004.02.26 |
申请人 |
LEE KEUN-HO;LEE CHANG-SUB |
发明人 |
LEE KEUN-HO;LEE CHANG-SUB |
分类号 |
G11C11/40;G11C11/00;G11C16/02;H01L27/24;(IPC1-7):G11C11/00 |
主分类号 |
G11C11/40 |
代理机构 |
|
代理人 |
|
主权项 |
|
地址 |
|