发明名称 Apparatus and method for translating an address in a non-contiguous memory block
摘要 A method and apparatus for non-contiguous translation protection table that includes one or more first registers, two or more second registers, an address translator, and a detector. Each first register contains a value denoting a size of each of two or more blocks of memory. Each second register contains a value denoting the starting physical address of an associated one of the two or more blocks of memory. The address translator receives a virtual address and translates the virtual address to a physical address of one of the two or more blocks of memory. The detector detects whether the received virtual address is outside of the range of the two or more blocks of memory. The blocks of memory may be translation protection tables that reside in physically non-contiguous memory locations.
申请公布号 US2004168038(A1) 申请公布日期 2004.08.26
申请号 US20040788777 申请日期 2004.02.27
申请人 INTEL CORPORATION 发明人 COLLINS BRIAN M.;REOHR DICK
分类号 G06F12/10;G06F12/14;(IPC1-7):G06F12/08 主分类号 G06F12/10
代理机构 代理人
主权项
地址