发明名称 |
Stratum clock state machine multiplexing switching |
摘要 |
Systems and methods are described for a core sync module. A method includes receiving a pair of input clock signals; utilizing a stratum clock state machine to control a multiplexer; utilizing the multiplexer to switch an input of a main clock between each of the pair of input clock signals; inducing a phase build-out activity; and transmitting an output clock signal. An apparatus includes a first input clock digital phase-locked loop; a second input clock digital phase-locked loop; a stratum clock state machine coupled to the first input clock digital phase-locked loop and to the second input clock digital phase-locked loop; and a main clock phase-locked loop coupled to the first input clock digital phase-locked loop, to the second input clock digital phase-locked and to the stratum clock state machine.
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申请公布号 |
US2004164782(A1) |
申请公布日期 |
2004.08.26 |
申请号 |
US20040782441 |
申请日期 |
2004.02.19 |
申请人 |
ZAMPETTI GEORGE;HAMILTON BOB |
发明人 |
ZAMPETTI GEORGE;HAMILTON BOB |
分类号 |
H03L7/07;H04J3/06;(IPC1-7):H03L7/06;G06F1/04;H03K3/013 |
主分类号 |
H03L7/07 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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