| 摘要 |
A transport stream is received and recorded, and the recorded transport stream is reproduced normally. A cycle timer generates a time stamp based on a clock generated by means of a clock generation circuit that is independent of the system clock generated by means of a built-in PLL of an AV decoder, a receiver adds the time stamp to a TS packet, and the TS packet is recorded in a hard disk. On the other hand, a transmitter supplies the TS packet read out from the hard disk to the AV decoder by way of a switch, MVLink-IC, DEMUX, and FIFO memory at the timing so that the time interval between adjacent TS packets is coincident with that of the time when it was received based on the time stamp added to the TS packet. |
