发明名称 Synchroniserende schakelingen en werkwijze voor analoog-naar-digitaal omzetters met parallelle weg.
摘要 An Analog-to-Digital (A/D) converter includes signal paths that are responsive to an analog input signal, to generate a multi-bit digital signal. A respective signal path includes a comparator. A synchronizing circuit is responsive to a clock signal and outputs of the comparators, to generate a respective delayed clock signal that is applied to a respective comparator. A respective signal path also includes a respective decoder that is responsive to a respective comparator and to the clock signal.
申请公布号 NL1025372(A1) 申请公布日期 2004.08.12
申请号 NL20041025372 申请日期 2004.01.30
申请人 SAMSUNG ELECTRONICS CO., LTD. 发明人 SOO-HYOUNG LEE
分类号 G06F3/05;H03M1/06;H03M1/08;H03M1/36 主分类号 G06F3/05
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