| 摘要 |
FIELD: microelectronics; large-scale integrated circuits built around bipolar transistors. ^ SUBSTANCE: proposed method for manufacturing bipolar transistor includes application of first insulator layer on substrate, formation of base windows in this layer by reactive ion etching, deposition of first polycrystalline silicon layer, doping of the latter with impurity of first polarity of conductivity, and deposition of second insulator layer whose thickness amounts to minimum two superposition errors on mask.. Photoresist mask is produced so that boundaries of emitter windows in photoresist occur above vertical sections of second insulator layer formed on base window steps and are disposed not closer than one superposition error on mask from each side wall of insulator vertical sections. Method also includes reactive ion etching of second insulator layer on horizontal sections of photoresist windows up to exposure of first polycrystalline silicon layer, etching of first polycrystalline layer up to exposure of silicon, doping of the latter with impurity of first polarity of conductivity, formation of wall insulator isolating ends of first polycrystalline silicon layer in emitter windows, deposition of second polycrystalline silicon layer, its doping with impurity of second polarity of conductivity, formation of passive and active base and emitter regions, formation of their contacts, and metallization. Thin film of silicon oxide is formed by oxidation on silicon surface prior to deposition of first polycrystalline silicon layer. Reactive plasma etching is used for etching first polycrystalline silicon layer up to exposure of first thin layer of silicon oxide, the latter is subjected to wet etching up to exposure of silicon, and it is partially made under first polycrystalline silicon layer. Wall insulator that serves to isolate ends of first polycrystalline silicon layer is formed by depositing third polycrystalline silicon layer followed by its oxidation up to silicon exposure, whereupon oxide produced by oxidation of third polycrystalline silicon layer is removed by reactive plasma etching on window bottom only. ^ EFFECT: provision for scaling size of bipolar transistor emitter and base thereby enhancing quality and yield. ^ 6 cl, 12 dwg |
