GATE PATTERN FORMATION THREE-LAYER HARD MASK FOR MANUFACTURING COMPLEMENTARY METAL-OXIDE SEMICONDUCTOR (CMOS) TRANSISTOR

摘要

PROBLEM TO BE SOLVED: To provide an integrated circuit that uses a process consolidation combining the substitution gate process using a three-layer hard mask consumed during the process and source/drain silicides. SOLUTION: In the process, a first temporary gate sidewall spacer defines a rising source/drain formation area, a second temporary spacer defines a source/drain injection and source/drain silicification area, and the temporary gate is protected from being silicified by the hard mask. COPYRIGHT: (C)2004,JPO&NCIPI