发明名称 Test method and architecture for circuits having inputs
摘要 A test method for a plurality of circuits respectively having inputs for greatly reducing the required test time and the control circuit complexity is provided. The method includes steps of providing a set of test patterns for detecting a characteristic of the circuits, providing a common data line, and electrically connecting the circuit inputs to the common data line so that the test pattern can be broadcasted to the circuits through the common data line. The present invention also provides an architecture for implementing such method.
申请公布号 US2004153921(A1) 申请公布日期 2004.08.05
申请号 US20030441691 申请日期 2003.05.19
申请人 NATIONAL SCIENCE COUNCIL 发明人 LEE KUEN-JONG;CHEN JIH-JEEN;HUANG CHENG-HUA
分类号 G01R31/3185;(IPC1-7):G01R31/28 主分类号 G01R31/3185
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