| 摘要 |
PROBLEM TO BE SOLVED: To reduce electric power consumption and a clock skew in a clock synthesis of a semiconductor integrated circuit by predicting inter-wiring capacitance and wiring delay of a clock line after wiring with high accuracy, and allowing wiring handling and the clock synthesis under consideration thereof. SOLUTION: In a clock synthesis process comprising a clock wiring interval specification process, an inter-wiring capacitance database production process and a clock tree synthesis process, an optimum wiring interval of the clock line is specified on the basis of clock specifications, thereby, the inter-wiring capacitance is estimated to produce an inter-wiring capacitance database, a delay time of a clock supply path is calculated on the basis thereof, and a buffer for delay adjustment is inserted into the clock supply path to execute clock tree synthesis. When the clock skew after the wiring is large, search for a factor of the clock skew is executed in a wiring process. Based on its information, the wiring interval is reset, and rewiring is executed. COPYRIGHT: (C)2004,JPO&NCIPI
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