发明名称 |
SIGNAL EQUILIBRATION BETWEEN VOLTAGE REGIONS |
摘要 |
PROBLEM TO BE SOLVED: To provide a method to equilibrate a signal in a range of an IC design, having a plurality of voltage regions. SOLUTION: The signal is equilibrated at a top level over the voltage region by using a voltage tree. The average waiting time in each voltage region is calculated, by using signal waiting time of the worst case and the best case. The signal is equilibrated at other level of design by increasing the waiting time in each region, until reaching an objective level, based on the slowest average waiting time. COPYRIGHT: (C)2004,JPO&NCIPI
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申请公布号 |
JP2004214650(A) |
申请公布日期 |
2004.07.29 |
申请号 |
JP20030421683 |
申请日期 |
2003.12.18 |
申请人 |
INTERNATL BUSINESS MACH CORP <IBM> |
发明人 |
FRY THOMAS WALKER;MENARD DANIEL RICHARD;NORMAND PHILLIP PAUL |
分类号 |
G06F17/50;G06K19/077;H01L21/82;H01L21/822;H01L27/04;(IPC1-7):H01L21/822 |
主分类号 |
G06F17/50 |
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