发明名称 |
ANALOGUE/DIGITAL DELAY LOCKED LOOP |
摘要 |
<p>A delay locked loop operates over a wide range of frequencies and has high accuracy, small silicon area usage, low power consumption and a short lock time. The DLL combines an analog domain and a digital domain. The digital domain is responsible for initial lock and operational point stability and is frozen after the lock is reached. The analog domain is responsible for normal operation after lock is reached and provides high accuracy using smaller silicon area and low power.</p> |
申请公布号 |
WO2004059846(A1) |
申请公布日期 |
2004.07.15 |
申请号 |
WO2003CA02040 |
申请日期 |
2003.12.29 |
申请人 |
MOSAID TECHNOLOGIES INCORPORATED;VLASENKO, PETER;HAERLE, DIETER |
发明人 |
VLASENKO, PETER;HAERLE, DIETER |
分类号 |
H03D3/24;H03L7/081;H03L7/087;H03L7/089;H03L7/095;H03L7/10;(IPC1-7):H03L7/087 |
主分类号 |
H03D3/24 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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