| 摘要 |
PROBLEM TO BE SOLVED: To provide an output control signal generating method of a synchronous semiconductor memory, and a semiconductor memory related to the method. SOLUTION: In a synchronous semiconductor memory which includes an output control signal generation circuit which generates a data output control signal in response to an internal clock signal, an output control clock signal and a column address strobe (CAS) latency signal, the output control signal generation circuit shifts read-out information signals continuously in response to the internal clock signal and the output control clock whose source clocks are common and generates one of shifted read-out information signals as an output control signal which directs a data output period in response to the CAS latency signal. As a result, the influence of clock jitter is decreased by synchronizing source clocks of clock signals used in the output control signal generation circuit with each other. COPYRIGHT: (C)2004,JPO&NCIPI
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