| 摘要 |
PROBLEM TO BE SOLVED: To solve the problem that since it is impossible to describe a gate delay time table concerning only the inclination of a partial input waveform and an interval of a load capacitance, the table is made fine even beyond the block, and a simulation time required for preparing a timing library becomes very long. SOLUTION: In a first gate delay time table, concerning inclinations S3 and S4 of an input waveform to be made fine and load capacitance values C3 and C4 intervals, inclinations S5, S6, S7 and S8 of the input waveform and load capacitance C5, C6, C7 and C8 are defined as table indexes to prepare a second gate delay time table. The first gate delay time table is made to have the table indexes of load capacitance values C1 and C2 with respect to the inclination S3 of the input waveform and the load capacitance values C1 and C2 with respect to the inclination S4 of the input waveform. Thus, it is possible to prevent the gate delay time table points from being overlapped in the first and second gate delay time tables. COPYRIGHT: (C)2004,JPO&NCIPI
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