Efficient per-queue backpressure signaling

摘要

High-speed signaling pins are often at a premium in Field Programmable Gate Arrays and minimizing the number of high-speed signals crossing a midplane is desirable to simplify system design and improve reliability. The method disclosed herein provides a more pin-efficient high-speed data path interface with per-queue backpressure signaling than what is available in prior art, leading to reduced system design and manufacturing costs and improved performance. The invention improves upon an industry standard protocol, the SPI 4.2 protocol, for high speed data transmission between switching system components by adding advanced functionality from a widely supported standards proposal, the CSIX level 2. In doing so, the invention offers a hybrid of the two interfaces that is more pin-efficient than either of them.