| 摘要 |
<p><P>PROBLEM TO BE SOLVED: To provide a packet switching apparatus for reducing a data error caused in its high-speed signal interface by changing a clock frequency inside the apparatus on the basis of an error rate of main signal data. <P>SOLUTION: When an error rate calculated on the basis of the number of data errors counted by a data error count section 207 exceeds a threshold, an apparatus control card 208 instructs a switch card clock generating section 205 to reduce the clock frequency distributed in the apparatus. <P>COPYRIGHT: (C)2004,JPO</p> |
