| 摘要 |
PROBLEM TO BE SOLVED: To realize both functions of a sub-routine call processing capable of being multiplexed and a low-power loop processing reducing the power required for memory access while suppressing the increase of circuit scale. SOLUTION: This device comprises an address generation part 10 for generating an instruction address IP, an instruction memory part 20 for reading an instruction code MI on the basis of the instruction address, an instruction decode part 30 for decoding the instruction code and executing the instruction, and an address/instruction storage part 40 for retreating a return address when the decode result is a sub-routine call instruction, restoring the return address when the decode result is a return instruction from the sub-routine, and performing write and read of an instruction group from the instruction memory part 20 when the decode result is a low-power loop instruction. The circuit for multiple sub-routine call instruction and the circuit for low-power loop are shared to dispense with the instruction buffer exclusive for the low-power loop instruction, whereby the increase of circuit scale is suppressed. COPYRIGHT: (C)2004,JPO
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