发明名称 Method and system for handling data between a clock and data recovery circuit and a data processing unit in asynchronous networks
摘要 Method and system for handling data between a clock and data recovery circuit and a data processing unit in asynchronous networks. <??>The invention relates to a method for handling data between a clock and data recovery system CDR and a data processing unit DP of a telecommunications network node TNN of an asynchronous communications network, using a bit rate adaptation circuit BAS, the bit rate adaptation system BAS comprising a memory unit MEM with a write process circuit Wp controlled by the recovered clock Rclk and a read process circuit Rp controlled by the local clock Lclk wherein the bit rate adaptation system BAS also comprises a pointer synchronization controller PSC which, depending on the data detected on the input data signal DIb1 of the bit rate adaptation system BAS, sets the read and write pointers to a fixed initial address value. <??>The invention also relates to a bit rate adaptation circuit BAS, which implements the method described above and a Clock and Data Recovery system and a telecommunications network node TNN of an asynchronous network, which comprise a bit adaptation circuit BAS according to the invention. <IMAGE>
申请公布号 EP1432160(A1) 申请公布日期 2004.06.23
申请号 EP20020360358 申请日期 2002.12.18
申请人 ALCATEL 发明人 SUND, MATTHIAS;WOLDE, JUERGEN;KARSTAEDT, JOERG
分类号 H04J3/06;(IPC1-7):H04J3/06;H04L12/00 主分类号 H04J3/06
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