| 摘要 |
Abstract of the Disclosure A method of compressing bus-related model data for transistor-level timing arcs in a circuit timing model. Compressed model syntax and timing information are provided for the following node-to-node transistor level representations: many-to-many bitwise, many-to-many, one-to-many, and many-to-one. In the many-to-many bitwise embodiment, each of the consecutive start nodes is coupled to a different end node. In the many-to-many embodiment, the plurality of consecutive transistor-level timing arcs have consecutive start nodes on a first bus and consecutive end nodes on a second bus, and each of the consecutive start nodes is coupled to each of the consecutive end nodes. In the many-to-one embodiment, the plurality of consecutive transistor-level timing arcs have consecutive start nodes on a first bus and a common end node on a second bus. In the one-to-many embodiment, the plurality of consecutive transistor-level timing arcs have a common start node on a first bus and consecutive end nodes on a second bus.
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