| 摘要 |
PURPOSE: A test method and a test circuit of a semiconductor memory device are provided to obtain read data corresponding to one external address one to one, and thus to reduce test time. CONSTITUTION: The semiconductor memory device has a test circuit(11) and a RAM macro(12). The test circuit comprises a PLL control circuit(13), a PLLC(14), a high speed control signal generation circuit(15), a high speed address generation circuit(16), a high speed data generation circuit(17), a connection conversion circuit(18) and control buses(19-22). The PLL control circuit(13) controls the PLLC(14) through a control bus(19), on the ground of an external clock and an external chip select signal and an external write enable signal and a test conversion signal and an external address.
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