CLOCK SYNCHRONIZER USING TIME DIVISION MODULATION

摘要

PURPOSE: A clock synchronizer using a time division modulation is provided to reduce an error rate by reducing the number of components in a process for designing a hardware and a software. CONSTITUTION: A clock synchronizer using a time division modulation includes an operation mode decision unit, a clock multiplexer, a frequency divider, a coefficient start signal generation unit, a time division period generation unit, a time division decision unit, and a clock phase shift unit. The operation mode decision unit(220) includes two modules performing alternately an active mode and a standby mode. The clock multiplexer(210) is used for outputting one of output clocks of two modules as a source clock according to an operation mode signal. The frequency divider(250) generates a frequency division clock to perform a time division process for the source clock. The coefficient start signal generation unit(280) decides a starting point of the time division process by using the frequency division clock. The time division period generation unit(270) performs the time division process for the source clock within one clock by a coefficient start signal and generates a time division period of the source clock. The time division decision unit(230) decides a phase shift degree of the source clock. The clock phase shift unit(240) generates a phase shift synchronization clock by using the time division period and the phase shift signal.